`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/18 11:51:01
// Design Name: 
// Module Name: moore_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module moore_top(
    input rst_i,
    input clk_i,
    input set_i,
    input [7:0] data_i,
    output reg detect_o/*,
    output reg [7:0] led*/
    );
    
	wire clk_div;
	
	reg [2:0] status = 3'b0;
    reg [7:0] read_buf = 8'b0;
	
	divider_1hz DIVIDER(clk_i, clk_div);
	
	always @(posedge clk_div or posedge rst_i) begin
		if (rst_i==1'b1) begin
			status = 3'b0;
		end else if (set_i) begin
			status = 3'b0;
			read_buf <= data_i;
		end else if (status==3'd0) begin
			status = read_buf[7] ? 3'd0 : 3'd1;
		end else if (status==3'd1) begin
			status = read_buf[7] ? 3'd2 : 3'd1;
		end else if (status==3'd2) begin
			status = read_buf[7] ? 3'd0 : 3'd3;
		end else if (status==3'd3) begin
			status = read_buf[7] ? 3'd4 : 3'd1;
		end else if (status==3'd4) begin
			status = read_buf[7] ? 3'd5 : 3'd3;
		end else if (status==3'd5) begin
			status = read_buf[7] ? 3'd0 : 3'd1;
		end
		
		read_buf = read_buf << 1;
	end
	
	always @(status) begin
	   if (rst_i | set_i) begin
	       detect_o = 'b0;
	   end else begin
	       detect_o = status=='d5 ? 'b1 : detect_o;
	   end
	end
    
endmodule
